MAX5980EVKIT#【PDF 20/49 页】EVAL KIT MAX5980

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Quad, IEEE 802.3at/af PSE Controller

for Power-over-Ethernet

V SENSE_ - V EE

V SU_LIM

212.5mV

V SU_LIM

106.25mV

V TH_FB

35mV

CLASS 4

CLASS 0 –3

V FLBK_ST

18V

V FLBK_ST

32V

V FLBK_END

46V

V OUT_ - V EE

Figure 3. Foldback Current Characteristics

Foldback Current

During startup and normal operation, an internal cir-

cuit senses the voltage at OUT_ and when necessary

reduces the current-limit clamp voltage (V SU_LIM ) to help

reduce the power dissipation through the external FET.

When I LIM_ = 80h (Classes 0–3), foldback begins when

V OUT_ - V EE > 32V; and when I LIM_ = C0h (Classes 4

and 5), foldback begins when V OUT_ - V EE > 18V. The

V SU_LIM eventually reduces down to the mini-

mum current-limit threshold (V TH_FB = 35mV) when

V OUT_ - V EE > 46V (Figure 3).

MOSFET Gate Driver

Connect the gate of the external n-channel MOSFET to

GATE_. An internal 50 F A current source pulls GATE_ to

(V EE + 10V) to turn on the MOSFET. An internal 40 F A

current source pulls down GATE_ to V EE to turn off the

MOSFET.

The pullup and pulldown current controls the maximum

slew rate at the output during turn-on or turn-off. Use the

following equation to set the maximum slew rate:

fast pulldown current increases with the amount of over-

shoot, and the maximum fast pulldown current is 50mA.

During turn-off, when the GATE_ voltage reaches a value

lower than 1.2V, a strong pulldown switch is activated to

keep the MOSFET securely off.

Interrupt

The device contains an open-drain logic output ( INT ) that

goes low when an interrupt condition exists. The Interrupt

register (R00h, Table 6) contains the interrupt flag bits and

the Interrupt Mask register (R01h, Table 7) determines

which events can trigger an interrupt. When an event

occurs, the appropriate Interrupt Event register bits (in

R02h to R0Bh) and the corresponding interrupt (in R00h)

are set to 1 and INT is asserted low (unless masked).

If the master device on the I 2 C bus sends out an Alert

Response Address, any MAX5980 device on the bus that

has INT asserted will respond (see the Global Addressing

and the Alert Response Address (ARA) section).

As a response to an interrupt, the controller can read

the status of the event register(s) to determine the cause

= GATE_

? V OUT_

? t

I

C GD

of the interrupt and take appropriate action. Each inter-

rupt event register is paired with a Clear-on-Read (CoR)

register. When an interrupt event register is read through

where C GD is the total capacitance between the gate

and the drain of the external MOSFET. The current limit

and the capacitive load at the drain control the slew

rate during startup. During current-limit regulation, the

device manipulates the GATE_ voltage to control the

voltage at SENSE_ (V RSENSE_ ). A fast pulldown activates

if V RSENSE_ overshoots the limit threshold (V SU_LIM ). The

20

the corresponding CoR register, the corresponding

event register is reset to 0 (clearing that interrupt event).

INT remains low and the interrupt is not reset when the

Interrupt Event register is read through the read-only

address. For example, to clear a supply event fault read

R0Bh (CoR) not R0Ah (read-only, see Table 12). Use the

INT_CLR bit (R1Ah[7], Table 27) to clear an interrupt, or

the RESET_IC bit (R1Ah[4]) to initiate software resets.

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